Voltage detection circuit composed of at least two MOS transistors

ABSTRACT

A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage V DD  via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage V DD  with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.

BACKGROUND OF THE INVENTION

The present invention relates to an improvement in a voltage level detection circuit which senses whether a power source voltage drops below a given voltage level.

A typical prior art voltage level detection circuit as shown in FIG. 1 is well known. In the drawing T₁ through T₄ designate MOS transistors, R₁ and R₂ designate resistors, P designates a P-channel type MOS transistor, and N designates an N-channel type MOS transistor. T₂ and T₄ form an inverter circuit. In addition, E₁ represents a power source voltage such as a battery with the cathode connected with a utility circuit and the anode grounded, and E₂ and E₃ represents potentials at respective nodes.

When the power voltage E₁ is increased above the threshold voltage VH₃ of the MOS transistor T₃, the transistor T₃ is turned ON and E₂ is increased to the ground potential. This means that the transistor T₁ is turned ON too and the drain potential E₃ of T₁ is equal to the power source voltage E₁ . In other words, the illustrated circuit compares the power source voltage E₁ with the threshold voltage of the P channel or N channel MOS transistor and then detects a drop in the power source voltage. FIGS. 4(a) and 4(b) are voltage characteristic charts showing a relationship between the voltages E₁ and E₂. However, design of such a circuit arrangement is relatively difficult because the MOS transistor should be driven in a normal mode up to near the threshold voltage level. Therefore, the resistor R₁ is smaller and the decision level E₁ is higher in practical use as depicted by the broken line in FIGS. 4(a) and 4(b ). This approach, however, results in increase of current flowing through the resistor R₁ and the transistor T₃ and in other words, increase of consumption current. The battery is often renewed.

Accordingly, it is an object of the present invention to provide a voltage level detection circuit with less power consumption.

In accordance with the voltage level detection circuit of the present invention, a power source voltage is compared with reference to the threshold voltage of an MOS transistor and the results of such comparison are developed as voltage level detection outputs. The level detection circuit is comprised of a first MOS transistor having the gate and the drain connected together with a power source voltage V_(DD) (E₁) via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the drain grounded via a resistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and novel features of the present invention as set forth in the appended claims and the present invention as to its organization and its mode of operation will best be understood from a consideration of the following detailed description of the preferred embodiments taken in connection with the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a prior art voltage level detection circuit;

FIG. 2 is a circuit diagram of an embodiment of a voltage level detection circuit embodying the present invention;

FIG. 3 is a circuit diagram of another embodiment of the present invention;

FIGS. 4(a), 4(b), 5(a) and 5(b), 6(a) through 6(c) are diagrammatic charts showing respective node potentials against a power voltage E₁ ;

FIG. 7 is a circuit diagram of an example of application of the present invention;

FIG. 8 is a diagrammatic chart showing a node potential V_(out) against the power source voltage V_(DD) (E₁); and

FIGS. 9 and 10 are circuit diagrams using modifications in the embodiment of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 illustrates a circuit diagram of an embodiment of the present invention whih includes a first MOS transistor T₇ having the gate and the drain connected together with a power supply voltage E₁ via a resistor R₃ and the source grounded and a second MOS transistor T₅ having the gate connected with the drain of the first MOS transistor T₇ and the drain grounded via a resistor R₄. The drain of the second MOS transistor T₅ is connected with the gate of an inverter composed of a couple of MOS transistors T₆ and T₈. The inverter drives voltage detection outputs.

FIGS. 5(a) and 5(b) show the drain voltage E₄ of the MOS transistor T₇ and the drain voltage E₅ of the MOS transistor T₅ against the power supply voltage E₁. If the power supply voltage E₁ is below the threshold voltage VH₇ of the MOS transistor T₇, then the MOS transistor T₇ is turned OFF with E₄ being the same as the potential E₁.

When E₁ is increased above the threshold voltage of T₇, this makes the gate voltage E₄ of T₅ fixed near the threshold voltage VH₇ as shown in FIG. 5(a). If a potential difference between E₁ and E₄ is below the threshold voltage VH₅ of T₅, T₅ remains in the OFF state and E₅ remains at the ground potential.

Thereafter, the difference between E₁ and E₄ exceeds the threshold voltage VH₅ of T₅ so that T₅ is turned ON and E₅ is equal to E₁ as shown in FIG. 5(b). It is obvious from FIG. 5(a) that E₄ is kept at a fixed level as long as the threshold voltage of T₇ is reached and that a potential variation in E₅ is developed at a sum of the P channel and N channel threshold voltages. This voltage value corresponds to a detection level. Therefore, by corresponding a desired driving voltage to the threshold voltages of the respective transistors it is able to sense drop in the power supply voltage.

The above-mentioned resistors R₃ and R₄ are load resistors for the MOS transistors T₇ and T₅. These resistance values may be high enough to avoid unstable operation by noise, etc., so that current flowing through T₇ and T₅ is remarkably small. As a result, less power consumption voltage detection is achieved.

FIG. 3 shows a circuit diagram of another embodiment of the present invention wherein a series circuit of resistors R₅ and R₆ is provided instead of the resistor R₃ of FIG. 2 and the junction of R₅ and R₆ is connected with the gate of an MOS transistor T₉. The remaining portion is identical with the implementation shown in FIG. 2.

When a potential difference between the power supply voltage E₁ and the gate voltage E₇ of the MOS transistor T₉ exceeds the threshold voltage VH₉ of the MOS transistor T₉, voltage detection is achieved. The gate potential E₇ is a potential divided by the resistors R₅ and R₆ and more particularly a portion of the potential difference between the power supply voltage E₁ and the drain voltage E₆ of a MOS transistor T₁₁ which is determined by a division ratio of the resistors R₅ and R₆. The gate potential E₇ is therefore higher than the potential E₄ as shown by FIG. 2. This implies that the detection level is higher than that in the circuit of FIG. 2.

FIGS. 6(a) through 6(c) show variations of potentials E₆, E₇ and E₈ at respective nodes as a function of the power supply voltage E₁. Although in FIG. 6(c) E₈ is varied from the zero level at a much higher level E₁ than that in FIG. 5(b), the amplitude of E₁ is optionally selectable by proper choice of the ratio of the resistor R₅ and R₆. Therefore, the detection level is also selectable. It will be noted that an MOS transistor T₁₂ is the substitution for the resistor R₄ of FIG. 2. In this case, such MOS resistor occupies a reduced area in implementating the circuit with the LSI technology.

The voltage level detection outputs can be utilized in a wide range of applications. An example of an application to an initial condition setting circuit is illustrated in FIG. 7 wherein T₂₁ through T₂₉ are C-MOS transistors and P designates P-channel transistors and N designates N-channel transistors. This includes a first MOS transistor T₂₅ having the drain and the gate connected together with a power supply voltage V_(DD) via a resistor R₂₂ and the source grounded and a second MOS transistor T₂₁ having the gate connected with the drain of the first MOS transistor T₂₅, the source connected with the power supply voltage V_(DD) and the drain grounded via a resistor R₂₃ and connected with the gates of T₂₂ and T₂₆ forming a C-MOS inverter. The output of the inverter is coupled with a set input or a reset input of a directly coupled flip-flop composed of T₂₃, T₂₄, T₂₈ and T₂₉. The output of the flip-flop serves as an initial condition setting signal ACL. A gate signal R.sub. 5 of T₂₇ is to reset the flip-flop. The power supply potential V_(DD) is negative.

A relationship between V_(DD) and the drain potential of T₁ is shown in FIG. 8. T₂₂ and T₂₆ are inverted when V_(DD) is increased above a sum of the threshold voltage V_(TH)(P) of the P-channel transistor T₂₅ and that V_(TH)(N) of the N-channel transistor T₂₁. Since the drain potential of T₂₁ is utilized as the set input of the flip-flop, the output ACL of the flip-flop bears the ground potential when the drain of T₁ is at the ground potential. If the drain of T₁ is at the potential V_(DD), no set input is developed so that the flip-flop remains in the previous condition until the reset signal R₅ is applied to the gate of the transistor T₂₇. Therefore, when the power supply voltage V_(DD) is below the sum of the threshold voltages, the ACL signal bears the ground potential and is impressed on other flip-flops or a register in order to establish an initial condition.

FIG. 9 is a modification of the embodiment shown in FIG. 7 wherein the resistor R₂₂ of FIG. 7 is divided into two resistors R₂₄ and R₂₅ and the junction of the resistors R₂₄ and R₂₅ is connected with the gate of a transistor T₃₀. A transistor T₃₅ is the substitution for the resistor R₂₃ of FIG. 7. FIG. 10 shows MOS transistors T₄₀ and T₄₁ provided instead of the resistors R₂₄ and R₂₅ of FIG. 9. In design of an LSI, a ratio of T₄₀ and T₄₁ can be varied to change the detection level.

While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed. 

What is claimed is:
 1. A voltage level detection and switching circuit comprising:a first MOS transistor; a second MOS transistor; a power source providing a source voltage; means for comparing the source voltage with the sum of the threshold voltage levels of said first and second MOS transistors; a flip-flop coupled to said comparison means, the output of said flip-flop being utilized as an initial condition setting signal; means for setting or resetting said flip-flop when the power source voltage exceeds the sum of the threshold voltage levels of said first and second MOS transistors.
 2. A circuit in accordance with claim 1, wherein said comparison means comprises:means connecting the gate and drain of said first MOS transistor together; a resistor connected between said power source and the drain of said first MOS transistor; means for connecting the source of said first MOS transistor to ground; means for connecting the gate of said second MOS transistor with the drain of said first MOS transistor; and means for grounding the drain of said second MOS transistor via a resistor.
 3. A circuit means in accordance with claim 2, wherein said resetting means comprises a P-channel transistor responsive to a reset signal.
 4. A circuit in accordance with claim 1, wherein said comparison means comprises:means for connecting the gate and the drain of said first MOS transistor together; two resistors connected in series between the power source and the drain of said first MOS transistors; means for grounding the source of said first MOS transistor; means for connecting the gate of said second MOS transistor to a junction between said two series resistors in the drain circuit of said first MOS transistor; and means for connecting the drain of said second MOS transistor to ground via a third transistor.
 5. A circuit means in accordance with claim 4, wherein said resetting means comprises a P-channel transistor responsive to a reset signal.
 6. A circuit in accordance with claim 1, wherein said comparison means comprises:means for connecting the gate and the drain of said first MOS transistor together; two transistors in series connected between the drain of said first MOS transistor and said power source; means for connecting the source of said first MOS transistor ground; means for connecting the gate of said second MOS transistor to a junction between said two series transistors in the drain circuit of said first MOS transistor; and transistor means for connecting the drain of said second MOS transistor to ground.
 7. A circuit means in accordance with claim 6, wherein said resetting means comprises a P-channel transistor responsive to a reset signal. 